1. Field of the Invention
The present invention relates to a liquid crystal display device. More particularly, the present invention relates to a liquid crystal display panel capable of minimizing crosstalk by using a parasitic capacitor between a pixel electrode and a data line.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) controls the light transmittance of liquid crystal with dielectric anisotropy by using an electric field to display a picture. To this end, the LCD includes a liquid crystal display panel having liquid crystal cells arranged in a matrix, and a drive circuit for driving the liquid crystal display panel.
The drive circuit for the liquid crystal display drives the liquid crystal display panel in an inversion driving method to improve display quality as well to prevent the liquid crystal from deteriorating. The inversion driving method includes a frame inversion system, a line (or column) inversion system, and a dot inversion system.
In the dot inversion driving method, the polarities of the liquid crystal cells are opposite to those of an adjacent liquid crystal cells in a horizontal and a vertical direction, and are inverted for each frame. The dot inversion driving method may provide a picture with a better quality than other inversion methods because flickers that may occur in the horizontal and vertical direction offset each other.
However, the dot inversion driving method has a disadvantage because the polarity of the pixel voltage signal applied from the data driver to the data line is inverted in the horizontal and vertical direction, an amount of the fluctuation of a pixel signal, i.e., the frequency of a pixel signal, is higher than that of the other inversion methods, thus power consumption is high.
To solve the problem of the high power consumption in the dot inversion method, a liquid crystal display which is adaptive to drive the liquid crystal cells in the dot inversion system while driving data lines in a column inversion system as shown in FIG. 1 have been proposed.
Referring to FIG. 1, the liquid crystal display includes a liquid crystal display panel 12 having a liquid crystal cell matrix, a gate driver 14 driving gate lines GL1 to GLn of the liquid crystal display panel 12, a data driver 16 driving data lines DL1 to DLm+1 of the liquid crystal display panel 12, and a timing controller 18 controlling the gate driver 14 and the data driver 16.
The liquid crystal display panel 12 includes liquid crystal cells, each having a thin film transistor TFT formed at each crossing of the gate lines GL1 to GLn and the data lines DL1 to DLm+1, and a pixel electrode PXL. The thin film transistor TFT applies a pixel signal from the data line DL to the pixel electrode PXL in response to a scan signal from the gate line GL. The pixel electrode PXL controls the transmittance of light by driving the liquid crystals, which are located between a common electrode (not shown) and the pixel electrode PXL, in response to the pixel signal. Such liquid crystal cells are alternately connected to the data lines DL, respectively, that are adjacent along a vertical direction through the thin film transistor TFT.
For example, the liquid crystal cells of odd-numbered horizontal lines connected to odd-numbered gate lines GL1, GL3, GL5, . . . are connected to the data line DL adjacent to their left, and receive the pixel signal. The liquid crystal cells of even-numbered horizontal lines connected to even-numbered gate lines GL2, GL4, GL6, . . . are connected to the data line DL adjacent to their right, and receive the pixel signal.
The timing controller 18 generates timing control signals that control the gate driver 14 and the data driver 16, and applies a pixel data signal to the data driver 16. Gate timing control signals generated in the timing controller 18 include a gate start pulse GSP, a gate shift clock signal GSC and a gate output enable signal GOE. Data timing control signals generated in the timing controller 18 include a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE and a polarity control signal POL.
The gate driver 14 sequentially applies scan signals to the gate lines GL1 to GLn in use of the gate timing control signals. Accordingly, the gate driver 14 drives the thin film transistors TFT on a horizontal line base in response to the scan signal.
The data driver 16 converts pixel data that is input to analog pixel signals and applies a horizontal line of pixel signals to the data lines DL1 to DLm+1 for each horizontal period when a scan signal is applied to the gate line GL. For example, the data driver 16 may convert the pixel data to the pixel signals using gamma voltages applied from a gamma voltage generator (not shown).
The data driver 16 applies the pixel signal in a column inversion driving system, thereby causing the pixel signal applied to the data line DL1 to DLm+1 to have an opposite polarity to that of the adjacent data line DL, and the polarity to be inverted for each frame. For instance, the data driver 16 applies the pixel signals with opposite polarities to each other to that of the odd-numbered data lines DL1, DL3, . . . , and the even-numbered data lines DL2, DL4, . . . , and inverts the polarity of the pixel signal applied to the data line DL1 to DLm+1 for each frame.
In this case, since the pixel electrode PXL are arranged in a zigzag pattern based upon the data lines DL1 to DLm+1, to which the pixel signal is applied by the column inversion system, the liquid crystal cells including the pixel electrode PXL are driven by a dot inversion system.
Specifically, the data driver 16 alternately changes an output channel of the pixel signal for each horizontal period in order to apply correct pixel signals to the pixel electrodes PXL which are arranged in a zigzag pattern along the data lines DL1 to DLm+1. In other words, in the event that the pixel signal is applied to the liquid crystal cells connected to the right hand of the data lines DL1 to DLm+1, the data driver 16 applies m-number of effective pixel signals to the first to mth data lines DL1 to DLm and applies a blank signal to the (m+1)th data line DLm+1. On the other hand, in the event that the pixel signal is applied to the liquid crystal cells connected to the left hand of the data lines DL1 to DLm+1, the data driver 16 shifts the m-number of effective pixel signals to the right by one channel and then applies the shifted pixel signals to the second to the (m+1)th data lines DL2 to DLm+1 and applies the blank signal to the first data line DL1. Herein, the blank signal represents a signal not defined.
The liquid crystal display has its picture quality improved by the liquid crystal cells driven by the dot inversion system, and the data driver 16 applies the pixel signal by the column inversion system, thus power consumption can be remarkably reduced as compared with that of when the pixel signal is applied in the dot inversion system.
However, in the liquid crystal display panel 12 shown in FIG. 1, there occurs a voltage deviation of a positive polarity or a negative polarity by parasitic capacitors Cdp formed between the data line DL and the pixel electrodes PXL adjacent to the data line DL. Particularly, the data line DL being driven by the column inversion system keeps continuously a polarity for one frame, so that the voltage deviation caused by the parasitic capacitor Cdp or the polarity is kept for one frame. As a result, a vertical crosstalk occurs. A reason for the vertical crosstalk will be discussed in detail with reference to FIGS. 2 and 3.
FIG. 2 illustrates a part of the liquid crystal display panel shown in FIG. 1, and FIG. 3 is a sectional view showing the liquid crystal display panel taken along line I-I′ shown in FIG. 2.
The parasitic capacitor Cdp shown in FIG. 2 includes a first parasitic capacitor Cdp1 located between a data line DLk and a left-hand pixel electrode P1 or P3, and a second parasitic electrode Cdp2 formed between the data line DLk and a right-hand pixel electrode P2 or P4. The data line DLk and the pixel electrodes P1 and P2 are located with the passivation film made of an inorganic insulating film or an organic insulating film therebetween, as shown in FIG. 3. The first parasitic capacitor Cdp1 and the second parasitic capacitor Cdp2 are formed in accordance with above result. The data line DLk is formed on a gate insulating film 22 on a lower substrate 20, and a semiconductor layer 24 is further formed, along the data line DLk, between the data line DLk and the gate insulating film 22.
Due to a coupling effect caused by the first and the second parasitic capacitors Cdp1 and Cdp2, a pixel signal supplied to the data line DLk and the pixel electrode P1 and P2 is distorted, which results in the display quality of the liquid crystal display panel being deteriorated. Specifically, the left-hand pixel electrode P1 and the right-hand pixel electrode P2 of the data line DLk are charged by pixel signals having polarities inverted from each other, to thereby generate a capacitance deviation between the first and the second parasitic capacitors Cdp1 and Cdp2. The capacitance deviation of the parasitic capacitors Cdp1 and Cdp2 keeps a polarity for one frame by the data line DLk to maintain the same polarity for one frame, to thereby interfere the data line DLk. As a result, a pixel signal on the data line DLk is distorted. The distorted signal on the data line DLk is induced to adjacent pixel electrodes P1 and P2, to thereby generate a vertical crosstalk and therefore to deteriorate the display quality.
Further, the data line DL and the pixel electrodes P1 and P2 are arranged a designated distance from each other in order to decrease the capacitance of the parasitic capacitor Cdp. As such, light leakage occurs from a backlight between the data line DL and the pixel electrodes P1 and P2 through the liquid crystal not driven. In particular, an amount of the light leakage between the data line DLk and the pixel electrodes P1 and P2 is produced in proportion to the capacitances of the parasitic capacitors Cdp1 and Cdp2. Accordingly, the amount of light leakage becomes different by the capacitance deviation between the first and the second parasitic capacitors Cdp1 and Cdp2. An asymmetric light leakage caused by the first and second parasitic capacitors induces a display quality that is more deteriorated.